1. Field of the Invention
The present invention generally relates to the field of fabricating integrated circuits, and more particularly relates to an apparatus and method for plating and/or polishing metal layers on semiconductor wafers.
2. The Related Art
Integrated circuits are widely applied in electronic industry. The integrated circuits are manufactured or fabricated on semiconductor material usually called semiconductor wafers. For forming electronic circuitry of the integrated circuits, the wafers may undergo such as multiple masking, etching, plating and polishing processes, and so on.
With the rapid development of the electronic industry, the demand on minisize, low power consumption and high reliability becomes inevitable to electronic products. Correspondingly, the integrated circuits which are as the key components of the electronic products must be improved for meeting the demand of the electronic products. In order to increase the power of the integrated circuits, one method is to decrease the feature size of the integrated circuits. In fact, the feature size of the integrated circuits has been quickly decreased from 90 nanometers to 65 nanometers, and now to 25 nanometers. Undoubtedly, the feature size of the integrated circuits will be further decreased with the improvement of the semiconductor technology.
However, one potential limiting factor to develop more powerful integrated circuits is the increasing signal delays at interconnections formed in the integrated circuits. As the feature size of the integrated circuits has decreased, the density of interconnections formed in the integrated circuits has increased. However, the closer proximity of interconnections increases the line-to-line capacitance of the interconnections, which results in greater signal delay at the interconnections. Generally, interconnection delays have been found to increase with the square of the reduction in feature size. In contrast, gate delays have been found to increase linearly with the reduction in feature size.
One conventional approach to compensate for this increase in the interconnection delay is to add more layers of metal. However, this approach has the disadvantages of increasing production costs associated with forming the additional layers of metal. Furthermore, these additional layers of metal can generate additional heat, which can be adverse to both chip performance and reliability.
Consequently, copper instead of aluminum has been widely used in the semiconductor industry to form the metal interconnections for copper has greater conductivity than aluminum. Also, copper is less resistant to electromigration than aluminum. However, before copper can be widely used by the semiconductor industry, new processing techniques are required. More particularly, a copper layer may be formed on a wafer using an electroplating process and/or etched using an electropolishing process. In the electroplating and/or electropolishing process, the wafer is held by a wafer chuck and an electrolyte solution is then applied on the wafer by a nozzle. A conventional electroplating and/or electropolishing apparatus has a nozzle with small size for ensuring the electroplating and/or electropolishing uniformity, which plating rate and/or removal rate is low. For improving the plating rate and/or removal rate, if only increase the size of the nozzle, the electroplating and/or electropolishing uniformity of the outer edge of the wafer will become worse. How to improve the plating rate and/or removal rate and at the same time ensure the electroplating and/or electropolishing uniformity of the outer edge of the wafer during the electroplating and/or electropolishing process is a challenge which needs to overcome.